The trend in advanced semiconductor packaging has been to reduce the form factor while improving electrical performance. This enables the creation of products for industry and consumers that are faster, cheaper and smaller. Through silicon vias (TSVs), or more accurately through silicon plugs (TSPs), provide an approach to achieve higher levels of integration and form factor reduction for advanced semiconductor packaging. As the name implies, the electrical connection of the back and front of a semiconductor device enables the possibility of vertically assembling multiple chips in a package where previously only one chip was present. Accordingly, more semiconductor devices can be integrated into a smaller form factor. In addition, different types of semiconductor chips can be also integrated in a single package to create a so-called system in a package (SIP). Irrespective of the approach, the footprint of multiple packages in the printed circuit board is reduced, which also reduces final product cost. Finally, interconnecting the chips by using TSVs can decrease the number of electrical connections necessary to the substrate [unit], because one substrate connection can service multiple chips. This also helps to simplify the assembly process and improve yield.
Silicon etch is a key process in TSV fabrication, since it is used to create deep TSVs in silicon substrates. It is within this context the following disclosure arises.